Content addressable memory (CAM) has been broadly used in many VLSI system applications such as imaging processing, network communication, and parallel data processing to facilitate operations of fast comparison and validation of patterns [J. B. Kuo and J. H. Lou, "Low-Voltage CMOS VLSI Circuits," John Wiley: New York, ISBN 0471321052, 1999]. As shown in FIG. 1, in a conventional 10T CAM cell [H. Kadota, J. Miyake, Y. Nishimichi, H. Kudoh, and K. Kagawa, "An 8-kbit Content-Addressable and Reentrant Memory," IEEE Journal of Solid-State Circuits, Vol. 20, No. 5, pp 951-957, 1985], it is composed of two portions: the SRAM portion (transistors M1-M6) and the tag-compare portion--transistors M7.about.M10 for performing the XOR operation of the data stored in the SRAM cell with the input data at the digit lines.
Said SRAM portion comprises two PMOS's, designated as M1 and M2; and four NMOS's, designated as M3, M4, M5 and M6, wherein a drain of the NMOS M3 is connected to that of the PMOS M1 at a first node n1 while their gates are tied together at a second node n2; a source of the PMOS M1 is connected to a supply voltage V.sub.DD ; a drain of the NMOS M4 is connected to that of the PMOS M2 at the second node n2 while their gates are tied together at the first node n1; a source of the NMOS M4 is grounded and that of the PMOS M2 is connected to the supply voltage V.sub.DD ; the NMOS M5 and NMOS M6 are pass transistors, one of them M5 is controlled by a word line WL via its gate, and its drain and source are connected to a first bit line BL and the first node n1 respectively; another one of them M6 is controlled by the word line WL via its gate, and its drain and source are connected to a second bit line BLB and the second node n2 respectively.
If logc-1 is stored at the internal storage node n1, which is different from the logic state of the data on the digit line (DL), then the match line (ML) is pulled down to ground, indicating a miss. Along with the increased complexity of the related VLSI systems, the speed performance of the tag-compare operation of a related large-size CAM circuit has become a bottleneck for high-speed applications, which is especially serious for operation using a low supply voltage. Recently, CMOS dynamic threshold (DTMOS) techniques have been reported for their advantages in low-voltage SOI CMOS VLSI circuits [F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, "Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI," IEEE Transactions on Electron Devices, Vol. 44, No. 3, pp 414-422, 1997; N. Lindert, T. Sugii, S. Tang and C. Hu, "Dynamic Threshold Pass-Transistor Logic for Improved Delay at Low Power Supply Voltages," IEEE Journal of Solid-State Circuits, Vol. 34, No. 1, pp 85-89, 1999; I. Y. Chung, Y. J. Park, and H. S. Min, "A New SOI Inverter Using Dynamic Threshold for Low-Power Applications," IEEE Electron Devices Letters, Vol. 18, No. 6, pp 248-250, 1997].